Allwinner T5

Allwinner T5 is a high-performance quad-core Cortex-A53 platform SoC for the new generation of automotive markets. Allwinner T5 is qualified for Automotive AEC-Q100 testing. It integrates Cortex-A53 quad-core CPU, G31 MP2 GPU, 32-bit DDR3/LPDDR3/DDR4/LPDDR4 DRAM, multi video output interfaces (RGB/2*LVDS/ HDMI/CVBS OUT), and multi video input interfaces (MIPI CSI/BT656/BT1120). It supports 4K@60fps H.265 decoder, 4K@25fps H.264 encoder, DI, 3D noise reduction, SmartColor system, and keystone correction module, providing smooth user experience and professional visual effect. Allwinner T5 can be used in IVI, digital cluster, HD AVM, HUD, and other intelligent cockpit products.

Quad-core ARM Cortex-A53@1.5GHz

G31 MP2

Support OpenGL ES 3.2/2.0/1.0, Vulkan 1.1, OpenCL 2.0

32-bit DDR4/DDR3/DDR3L/LPDDR3/LPDDR4 interface, supporting maximum capacity of 4GB

SD3.0/eMMC5.0 interface

8-bit Nand flash interface with maximum 80-bit/1KB ECC

H.265 MP decoder up to 4K@60fps

H.264 BL/MP/HP decoder up to 4K@30fps

VP9 decoder up to 4K@60fps

AVS2 decoder up to 4K@60fps

Multi-format 1080p@60fps video playback, including VP8, MPEG1/2 SP/MP, MPEG4 SP/ASP, AVS+/AVS JIZHUN, VC1 SP/MP

Two DAC channels and four ADC channels

Support 1 audio output interface (differential LINEOUTP/N or single-end LINEOUTL/LINEOUTR)

Support 2 audio input interfaces (stereo FMINR/L and stereo LINEINR/L)

One Audio HUB, supporting internal mixing function

Embedded 3 I2S/PCM (I2S0 for extended audio codec, I2S2 for BT, I2S3 for digital power amplifier)

Support Left-justified, Right-justified, Standard I2S mode, PCM mode, and TDM mode

I2S mode supports 8 channels, and 32-bit/192kbit sample rate

I2S and TDM modes support maximum 16 channels, and 32-bit/96kbit sample rate

One OWA IN/OUT interface, supporting 16-/20-/24-bit inputs and outputs

Integrated digital microphone, supporting maximum 8 digital PDM microphones

HDMI 2.0a up to 4K@60fps

TV CVBS output, supporting PAL/NTSC

LVDS interface with dual link, up to 1080p@60fps

RGB interface with DE/SYNC mode, up to 1080p@60fps

Support Full Disk Encryption

AES, DES, 3DES, and XTS encryption and decryption algorithms

MD5, SHA, and HMAC tamper proofing

RSA, ECC signature and verification algorithms

Support 160-bit hardware pseudo random number generator (PRNG) with 175-bit seed

Support 256-bit hardware true random number generator (TRNG)

Integrated 2K-bit EFUSE for chip ID and security application

3 x USB2.0 Host, 1 x USB2.0 OTG

2 x Ethernet MAC (one 10/100 Mbps Ethernet port with RMII interface, one 10/100/1000 Mbps Ethernet port with RGMII and RMII interfaces)

SDIO 3.0, TSC, SCR, CIR Receiver

6 x TWI, 2 x SPI, 6 x UART

6-ch PWM, 4-ch GPADC, 1-ch LRADC

Companion Allwinner Power Management IC

TFBGA 421balls

15 mm x 15 mm size, 0.65 mm ball pitch, 0.35 mm ball size

Process