Allwinner R853

High-performance AI vision processor

Overview

Allwinner R853 is a new generation high-performance and low-power processor SoC targeting at the field of intelligent vision. It can be widely used in intellectually upgraded industries such as intelligent door lock, intelligent attendance and access control, webcam, tachograph, and intelligent desk lamp.

Allwinner R853 integrates single Cortex-A7 core and RISC-V MCU. It is also designed with a new generation of high­-performance ISP image processor and Allwinner Smart video engine with maximum 5M@25fps H.265/H.264 encoding and 5M@25fps H.264 decoding to achieve professional picture effect. It has built-in NPU with maximum 1T computing power and supports INT8/INT16 hybrid operation and typical network models such as TensorFlow/MXNet/PyTorch/Caffe. Allwinner R853 has advanced 22nm techniques to support product miniaturisation design. It also supports various special video input and output interfaces such as 1 x 4-lane MIPI-CSI/DVP/MIPI-DSI/RGB to meet the needs of Al visual products. Allwinner R853 supports 16-bit DDR3/LDDR3L to meet the requirements of various products on high bandwidth. In addition, stable and easy-to-use matching reference design is available for Linux SDK as well as software and hardware to assist clients in rapid mass production of products.

Highlights

Integrate ARM Cortex-A7@1GHz, RSIC-V@600MHz, 1Tops NPU, and 16-bit DDR3/DDR3L at maximum frequency of 933MHz to meet the variable requirements of compute power and bandwidth

Support 5M@25fps H.264/H.265 video online real-time encoder, Allwinner new­ generation display engine ISP600, and the mainstream level in 2/3DNR, HDR, and edge enhancement

Parallel CSI and 4-lane MIPI CSI support maximum 4-ch AHD camera or 3-ch RAW data camera interleaved-input for video input

Rich peripheral interfaces including 5xTWI, 4xUART, 4xSPI, 4xGPADC, USB2.0 DRD, WIEGAND, and other interfaces that greatly facilitate product expansion

Block diagram

 

Specifications

 

CPU

Cortex-A7@1 GHz CPU core, supporting 32 KB I-cache, 32 KB D-cache, and 128 KB L2 cache

RISC-V@600 MHz core, supporting 16 KB I-cache and 16 KB D-cache

 

NPU

Maximum performance up to 1 Tops

Embedded 128KB internal buffer

Support deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN

 

Memory

16-bit DDR3/DDR3L interface, supporting maximum capacity of 1GB

SD3.0/eMMC 5.1 interface

SPI Nor/SPI Nand Flash

 

Video encoder

H.264/H.265 up to 4K@15fps or 5M@25fps

JPEG up to 1080p@60fps

 

Video decoder

Support H.264 BP/MP/HP, JPEG

Real-time multiple streams H.264 encoding capability: 5M@25fps

JPEG snapshot performance of 1080p@60fps independently

 

Display engine

Allwinner SmartColor post processing for an excellent display experience

Support 2 video channels and 1 UI channel

Support G2D hardware accelerator including rotate, mixer, scaler functions

 

Video input

ISP

- Maximum performance of 5M@30fps and maximum resolution of 3072 x 1772

- Adjustable 3A functions (AE, AWB, and AF), and 3A parameters are adjustable

- Provide ISP tuning tools for the PC

VIPP

- Four VIPP YUV422 or YUV420 outputs

- Maximum performance of 5M@30fps and maximum resolution of 3072 x 1772

8-/10-/12-/16-bit parallel CSI interface

- Supports digital camera (DC), BT.601, BT.656, BT.1120 protocol

- Maximum video capture resolution up to 5M@30fps

1x4-lane MIPI CSI interface

- Support DOL WDR mode and splitting into 2x2-lane MIPI CSI

- Support 4-ch VC de-interleaver function

- Maximum video capture resolution up to 5M@30fps

 

Video output

RGB LCD output interface up to 1920 x 1080@60fps

1x4-lane MIPI DSI interface up to 1920 x 1200@60fps

 

Audio

1 DAC and 2 ADCs

Analog audio interfaces: MICIN1P/N, MICIN2P/N, LINEOUTP/N

Digital audio interfaces: I2S/PCM x 2, DMIC

 

Security system

AES, DES, 3DES encryption and decryption algorithms

⁠RSA/ECC signature verification algorithm

MD5/SHA and HMAC tamper proofing

PRNG/TRNG hardware random number generator

Integrated 2 Kbits OTP storage space

 

Connectivity

USB2.0 DRD, SDIO 3.0, SPI x 4, UART x 4, TWI x 5, WIEGAND

PWM (12-ch), GPADC (4-ch)

10/100/1000M EMAC with RMII and RGMII interfaces

 

Package

LFBGA318, 12 mm x 12 mm body size, 0.5 mm ball pitch

 

Application diagram